1. Technical Field
Example embodiments relate to a semiconductor device having stress layers and a method of manufacturing the same, wherein surface damage to the active regions may be reduced or prevented during the stress layer formation process.
2. Description of the Related Art
Increasing the mobility of carriers in a material layer is being researched in an effort to develop higher integrated semiconductor devices. To increase the mobility of carriers, a tensile stress or a compressive stress may be applied to an active region by way of a stress layer. A tensile stress layer may be formed on an NMOS area where electrons may act as major carriers. A compressive stress layer may be formed on a PMOS area where holes may act as major carriers. To increase the effect of stress, a source/drain region of a PMOS area may be formed of SiGe, and a stress layer may be formed closer to a top surface of the active region.
However, a NMOS area and a PMOS area may have a gate spacer, thus resulting in a stress layer being formed on the gate spacer. Consequently, the stress layer may be distanced from the active region by a distance corresponding to the thickness of the gate spacer, which may render it more difficult to apply sufficient stress on the active region. Accordingly, it may be beneficial to form the stress layer after removing the gate spacer. However, etching damage may occur to the top surface of the active region, including the source/drain region, when removing the gate spacer. For example, a source/drain region made of SiGe in the PMOS area may be relatively vulnerable to the etching process and, thus, may be recessed more deeply than a source/drain region made of silicon.
A conventional method for forming stress layers of a semiconductor device will be described below with reference to the accompanying drawings. FIGS. 1A and 1B are longitudinal sectional views illustrating a conventional method of forming stress layers of a semiconductor device 100. Referring to FIG. 1A, the semiconductor device 100 may be manufactured by forming isolation regions 110 and well regions 115a and 115b in a substrate 105; forming gate patterns 120 including a gate insulating layer 121, a gate electrode 123, and a first gate spacer 125; forming source/drain regions 130a and 130b; forming second gate spacers 150; and forming silicide regions 140 and 145. Stress layers may be formed after forming the silicide regions 140 and 145. However, the second gate spacers 150 may distance the stress layers from the source/drain regions 130a and 130b of the substrate 105, thus reducing the desired stress effect. Accordingly, to ensure a sufficient stress effect, it may be beneficial to form the stress layers after removing the second gate spacers 150. However, damage to the active region may occur when removing the second gate spacers 150.
FIG. 1B is a longitudinal sectional view illustrating the damage caused during the removal of the second gate spacers 150. Referring to FIG. 1B, the top surfaces of the silicide regions 140a and 145a and the top surfaces of the source/drain regions may be recessed (R) and certain parts of the active regions may be deeply recessed or dented (D). Technical publications may be silent about this damage to the surfaces of the active regions.
For example, the second gate spacers 150 may be formed of silicon nitride. Because silicon nitride may be more rigid than other film materials used in a semiconductor fabrication, damage may occur to the other film materials during the removal of the second gate spacers 150. When the silicide regions 140a and 145a and the source/drain regions 130a and 130b are surface-recessed, conductive regions may be narrowed, thus increasing resistance and junction leakage. Additionally, if a process for removing the second gate spacers 150 is unsteady, the silicide regions 140a and 145a may be completely removed. Furthermore, when dents D are generated in the active regions, stronger electric fields or higher resistances may be generated locally, thus causing a punch-through phenomenon.